Q. A digital IC tester is designed using Intel 8085 to check Quad-NAND gates. Write a program to
test the IC and turn on the green LED if the IC is working properly else turn on the red LED. The
pin diagram of a NAND gate (7400) is shown below. The input pins (1A, 1B, 2A, 2B, 3A, 3B,
4A and 4B) of the gate are connected to output port 40H and the output pins (1Y, 2Y, 3Y and 4Y)
are connected to input port 30H. Also the green and red LEDs are connected to port 41H as
shown below.
soln
As per the 4 NAND gate input and output connections, the combination of inputs and their
desired output for the 4 gates would be as follows:
The outputs at port 41H are: 01H to turn on the green LED
02H to turn on the red LED
LXI H, D000H ; assign memory location for input data
MVI M, 00H ; store inputs 00H, 55H, AAH and FFH
INX H
MVI M, 55H
INX H
MVI M, AAH
INX
MVI M, FFH
INX H ; assign memory location for output data
MVI M, 0FH ; store outputs 0FH, 0FH, 0FH and 00H
INX H
MVI M, 0FH
INX H
MVI M, 0FH
INX H
MVI M, 00H
LXI B, D000H ; assign BC to store the address of inputs
LXI H, D004H ; assign HL to store the address of outputs
MVI D, 04H ; assign D to store the count for four data
LABEL: LDAX B ; get the input data from memory
OUT 40H ; send the input to the NAND gate
IN 30H ; get the output of NAND gate
ANI 0FH ; mask the higher nibble, (because higher nibble is not used)
CMP M ; check if the NAND gate gave desired output
JNZ END ; if no jump to end and turn on the red LED
INX H ; if yes check for next data, increase HL for next input data
INX B ; increase DE for new output data
DCR D ; decrement the count
JNZ LABEL ; if the count is not zero repeat
MVI A, 01H ; after all desired outputs are obtained for the input combinations
OUT 41H ; turn ON the green LED (the NAND gate is working properly)
HLT ; stop
END: MVI A, 02H ; if any of the input combination gives undesired output
OUT 41H ; turn on the red LED (NAND gate is not working properly)
HLT ; stop
test the IC and turn on the green LED if the IC is working properly else turn on the red LED. The
pin diagram of a NAND gate (7400) is shown below. The input pins (1A, 1B, 2A, 2B, 3A, 3B,
4A and 4B) of the gate are connected to output port 40H and the output pins (1Y, 2Y, 3Y and 4Y)
are connected to input port 30H. Also the green and red LEDs are connected to port 41H as
shown below.
soln
As per the 4 NAND gate input and output connections, the combination of inputs and their
desired output for the 4 gates would be as follows:
The outputs at port 41H are: 01H to turn on the green LED
02H to turn on the red LED
LXI H, D000H ; assign memory location for input data
MVI M, 00H ; store inputs 00H, 55H, AAH and FFH
INX H
MVI M, 55H
INX H
MVI M, AAH
INX
MVI M, FFH
INX H ; assign memory location for output data
MVI M, 0FH ; store outputs 0FH, 0FH, 0FH and 00H
INX H
MVI M, 0FH
INX H
MVI M, 0FH
INX H
MVI M, 00H
LXI B, D000H ; assign BC to store the address of inputs
LXI H, D004H ; assign HL to store the address of outputs
MVI D, 04H ; assign D to store the count for four data
LABEL: LDAX B ; get the input data from memory
OUT 40H ; send the input to the NAND gate
IN 30H ; get the output of NAND gate
ANI 0FH ; mask the higher nibble, (because higher nibble is not used)
CMP M ; check if the NAND gate gave desired output
JNZ END ; if no jump to end and turn on the red LED
INX H ; if yes check for next data, increase HL for next input data
INX B ; increase DE for new output data
DCR D ; decrement the count
JNZ LABEL ; if the count is not zero repeat
MVI A, 01H ; after all desired outputs are obtained for the input combinations
OUT 41H ; turn ON the green LED (the NAND gate is working properly)
HLT ; stop
END: MVI A, 02H ; if any of the input combination gives undesired output
OUT 41H ; turn on the red LED (NAND gate is not working properly)
HLT ; stop
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